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Project TitleRelief of Stress Caused by Thermal Expansion Mismatch Based on Air-Gapped SiO2 Templates Deposited Using Chemical Vapor Deposition
Track Code2011-097
Short Description

This technology is a novel method to mitigate the stress induced by thermal expansion coefficient mismatch for semiconductor devices.

Abstract

A SiO2 nanotemplate structure is used to block the threading dislocations and reduce the thermal stress due to thermal expansion coefficient mismatch between Ge and Si.

 
Tagsepitaxy, photodetector, semiconductor
 
Posted DateOct 6, 2011 11:48 AM

Researcher

Name
Sang Han
Darin Leonhardt
Swapnadip Ghosh

Manager

Name
Briana Wobbe

Background

High-quality germanium (Ge) grown directly on silicon (Si) (Ge-on-Si) heterostructures have been actively pursued for many advanced applications, including near-infrared photodetectors, high-mobility field effect transistors, and virtual substrates for integrating III-V multijunction solar cells.  However, growing epitaxial Ge on Si poses many engineering challenges, ranging from lattice mismatch, to thermal expansion coefficient mismatch, to non-planar morphological evolution.  The materials engineering solutions to circumvent the lattice mismatch include metamorphic growth, graded buffer layers, selective epitaxial overgrowth, and a variety of defect filtering strategies. 

Researchers at the University of New Mexico use silicon dioxide (SiO2) based templates with nanoscale windows placed between Ge and Si as well as within Ge epilayer to simultaneously overcome the lattice mismatch and relieve the film stress caused by the thermal expansion coefficient mismatch.  Since the geometrical factors, such as aspect ratio, pitch, and absolute dimensions, affect the level of stress coupling between layers, they have computationally explored these geometrical factors to determine the optimum template design for stress relief. 

Technology Description

This technology is a novel method to mitigate the stress induced by thermal expansion coefficient mismatch for semiconductor devices.  A SiO2 nanotemplate structure is used to block the threading dislocations and reduce the thermal stress due to thermal expansion coefficient mismatch between Ge and Si.   Unlike thermally grown SiO2, these SiO2 templates, inserted within the Ge layer by chemical vapor deposition and conventional dry etching, leave voids around the template sidewall and top surface, while allowing Ge to grow selectively over the template surface and relax.  These voids (or air-gap) around the template sidewalls and top surface relieve stress caused by the thermal expansion coefficient mismatch between the film and the substrate.

Advantages/Applications

  • Reduces the etch pit density compared to the etch pit densities observed on the Ge grown directly on Si.
  • Simultaneously overcomes the lattice mismatch and relieves the film stress caused by the thermal expansion coefficient mismatch.
  • Produces large areas of high-quality, lattice-mismatched materials on Si.
  • Potential applications include near-infrared photodetectors, high-mobility field effect transistors, virtual substrates for integrating III-V multijunction solar cells, and other semiconductor devices.

Publications

INQUIRES

STC has filed intellectual property on this exciting new technology and is currently exploring commercialization options. If you are interested in information about this or other technologies, please contact Arlene Mirabal at amirabal@stc.unm.edu or 505-272-7886.

Files

File Name Description
9,269,724 Issued Patent None Download
8,937,366 Issued Patent None Download

Intellectual Property

Patent Number Issue Date Type Country of Filing
9,269,724 Feb 23, 2016 Divisional United States
8,937,366 Jan 20, 2015 Utility United States