Go to Top
INVENTOR LOGIN

Details

Project TitleDefect Removal in Ge Grown on Si
Track Code2009-122
Short Description

This invention is a novel processing technology by which defects that form upon coalescence of islands (e.g., stacking faults and twins) can be eliminated.

Abstract

This invention is a novel processing technology by which defects that form upon coalescence of islands (e.g., stacking faults and twins) can be eliminated. This technology also complements the self-directed touch down fabrication (see 2004-009) to form low-defect-density lattice mismatched heteroepitaxial layer. The technology also describes methods for rectifying defects that form when lattice-mismatched epitaxial islands are grown on silicon by the touchdown technique as an exemplary application. Defect annealing technology would equally benefit other semiconductor islands coalescing after lateral overgrowth.

 
Tagsoptical, semiconductors
 
Posted DateAug 17, 2012

Researcher

Name
Sang Han
Darin Leonhardt

Manager

Name
Briana Wobbe

Background

Conventional semiconductor device fabrication is generally based on growth of lattice-matched layers. Over the past several years there has been increased interest in epitaxial growth of lattice-mismatched semiconducting material systems. Lattice mismatched systems can provide a greater range of materials characteristics than silicon. For example, the mechanical stress in a lattice mismatched layer and control of its crystal symmetry can be used to modify the energy band structure to optimize performance of optoelectronic devices. Lattice mismatched systems can also enable compound semiconductor devices to be integrated directly with Si-based complementary metal oxide semiconductor (CMOS) devices. This capability to form multifunction chips will be important to the development of future optical and electronic devices. The method includes forming an interface layer on a portion of a substrate. The plurality of seed pads then formed by “self-directed touchdown” by exposing the interface layer to a material comprising a semiconductor material (2004-009). Since the exposure to a semiconductor material naturally opens up the nanoscale windows in the interlayer without the use of high-resolution lithography, we have dubbed the self-templating growth technique as Germanium “touchdown” on Silicon. Semiconductor islands can then be selectively grown on the substrate through opening of the template. These islands can then be coalesced to form a single crystal epitaxial overgrowth layer. In essence, the touchdown technique provides a low-cost avenue, by eliminating the need for high-resolution lithography, to manufacture engineered substrates comprised of lattice-mismatched materials.

        

Stacking faults and first-order twins are observed within islands upon coalescence and result from stacking errors during growth on the smaller semiconductor islands. Upon island coalescence, complex moire fringes are observed contiguous to highly faulted planes within epitaxial layers grown on all four semiconductor substrate orientations and are attributed to multiple twinning. Stacking faults and cubic twin are able to fit the coincidence lattice in the region of the coalesced islands, and can hamper the functional properties of the material. Thus there is a need to overcome these defects during coalesce process to make defect free heteroepitaxial layers of lattice mismatched systems.

Technology Description

This invention is a novel processing technology by which defects that form upon coalescence of islands (e.g., stacking faults and twins) can be eliminated. This technology also complements the self-directed touch down fabrication (2004-009) to form low-defect-density lattice mismatched heteroepitaxial layer. The technology also describes methods for rectifying defects that form when lattice-mismatched epitaxial islands are grown on silicon by the touchdown technique as an exemplary application. Defect annealing technology would equally benefit other semiconductor islands coalescing after lateral overgrowth.

Advantages/Applications

  • Reduced stress-casing defects in the Ge-Si.
  • Improved quality in optoelectronic based films
  • Improved functionalization of semiconductor devices
  • Multifunction chips for the development of future optical and electronic devices.

INQUIRES

STC has filed intellectual property on this exciting new technology and is currently exploring commercialization options. If you are interested in information about this or other technologies, please contact Arlene Mirabal at amirabal@stc.unm.edu or 505-272-7886.

Files

File Name Description
8,242,003 Issued Patent None Download

Intellectual Property

Patent Number Issue Date Type Country of Filing
8,242,003 None Utility United States