Over the past several years there has been increased interest in epitaxial growth of lattice-mismatched semiconducting material systems. Lattice mismatched systems can provide a greater range of materials characteristics than silicon. For example, the mechanical stress in a lattice mismatched layer and control of its crystal symmetry can be used to modify the energy band structure to optimize performance of optoelectronic devices. Lattice mismatched systems can also enable compound semiconductor devices to be integrated directly with Si-based complementary metal oxide semiconductor (CMOS) devices. This capability to form multifunction chips will be important to the development of future optical and electronic devices.
Problems arise however, because an epitaxial layer of a lattice-mismatched material on a substrate is often limited to a critical thickness h(c), before misfit dislocations begin to form in the epitaxial material. For example, h(c) =2nm for a germanium epitaxial layer on a silicon substrate. Because of the relatively small h(c) and the large dislocation densities at thickness greater than h(c), use of the heteroepitaxial layer is impractical.
Thus there is a need to overcome these and other problems and provide a method to grow detect free heteroepitaxial layers of lattice mismatched systems.
The defect-free heteroepitaxy of Ge on Si has significant ramifications in integrating any lattice mismatched compound semiconductor devices (e.g., III-V and SiC optoelectronic devices) with Si-based complimentary metal oxide semiconductor (CMOS) devices. The Ge layer can alleviate the lattice mismatch that exists between Si and lattice mismatched layer (e.g., III-V and SiC compound semiconductors) as a buffer. The absence of threading dislocations and minimal stacking faults that terminate within 80 nm of the Ge-Si interface is such a promising result that its potential commercialization may impact a broad range of semiconductor manufacturing. For example, a clear advantage exists in reducing the manufacturing cost for III-V and SiC devices by eliminating the use of III-V and SiC wafers. Instead, one can grow a thin layer of these compound semiconductors on Si. Although the scale-up from laboratory scale samples to 12-inch Si wafer is going to be an engineering challenge, the defect-free Ge heteroepitaxy can potentially increase the throughput of III-V and SiC devices by 10 to 1000 orders of magnitude.
This invention is a method to produce defect free heteroepitaxy layers of lattice mismatched systems.
STC has filed intellectual property on this exciting new technology and is currently exploring commercialization options. If you are interested in information about this or other technologies, please contact Arlene Mirabal at email@example.com or 505-272-7886.